FPGA Development with wujian100 SoC - Part Three: Start a New Project on CDK

Post on 2020-03-29 09:19
Updated on 2020-03-29 01:00

Start a new project with CDK.

FPGA Development with wujian100 SoC

Part Three: Start a New Project on CDK

Author: 加一(Jiayi)

Something to say

Recently I participate a contest named Integrate Circuit Innovation Contest which requires me to use WJ100 developed by Ali Inc. team t-head and a FPGA develop board with Xlinx XC7A200TR3B Core. It’s not my first time to cope with FPGA but still, I find it difficult to interpret Verilog Code and make the FPGA works. Luckily, with the help of WJ100 Sdk and CDK(C-sky Develop Kit) which developed by Ali Inc. we could jump the Verilog and long waiting synthesizing part directly to use the pre-setted circuit and easy writing C to develop.

About WJ100

T-Head’s Wujian SoC Platform utilizes the cloud-terminal-integration design philosophy that fuses software and hardware. Full stack integration of chips, operating systems and algorithms enables customers to develop chip products that can be mass-production.

Low power consumption: User-defined power consumption scenarios, with standby power consumption of less than 1uA, and operating power consumption of less than 100uA/MHz

According to the official sites of t-head Inc., WJ100 is a low cost and high power efficiency SoC, which barely means that it could be easily deployed on any chips and consumes lower power.

However, as I talked before, it is a open source project and as I believed, the real function of this SoC is to simplify the use of FPGA and to offer the developer a brand new way to develop: integrate Soc and FPGA to deal with some projects which require both power efficiency and fast steady frequency.

related websites t-head

How to use WJ100 SoC

This tutorial is for those who utilize vivado to generate bitstream file and CDK to develop your own projects with Windows.

For Part 1 Bitsream Generation please refer to Part_1_Bitstream_Generation.
For Part 2 CDK Toolkit and wujian100 SDK please refer to Part_2_CDK_Toolkit&Wujian100_SDK.
For Part 3 Start a New Project on CDK please refer to Part_3_Start_a_New_Project_on_CDK
For Part 4 Hello World please refer to Part4_Hello_World
For Part 5 GPIO please refer to Part5_GPIO
For Part 6 UART please refer to Part6_UART
For Part 7 TIMER please refer to Part7_TIMER
For Part 8 Interrupt please refer to Part8_VIC

Part 3 Start a New Project on CDK

Open your CDK desktop.
Before create a new projeck, we need to create a new workspace for it. Click create a new multi-project workspace and choose your name and path. Finish the create of project.
After we have successfully created the workspace, we could now create a new project. Find Project on your toolbar and choose new project and there will be a new project window.
Since CDK doesn’t offer an template for wujian100, we must choose a core similar to wujian100 SoC. So let us choose Smartl_E902-BareMetal under ERISC Series. However, as I believe, whatever you choose are both alright because we are going to delete all the files and change almost every configuration later.
Remove every folder in the project you just created. Both in the workspace and in the folder. Be careful because you need to restore main folder and {yourprojectname}.cdkprj
Go to wujian100_open repo path and open sdk, copy following folders to ./{yourcdkprojectname}: board, csi_core, csi_driver, csi_kernel, libs, utilities. Open projects-examples-hello_world and copy config folder to ./{yourcdkprojectname}, just like:
Right click {yourprojectname} in the left side bar or wherever called project view window and choose add source folder option.
Add folders just moved to your project folder one by one and click NO for “copy source folder to current project path”.
Finally you should see the project view like this with 8 folders and all its contents are inside.
Open project menu on the toolbar and select open active project settings.
In target label under target info we could write our description about wujian100, i.e.
```
Core: wujian100 SoC
Board: Xilinx XC7A200TR3B
```

In Compiler label we need to modify include path, delete several include path related to the original template. The include path should be like the following.

$(ProjectPath)
$(ProjectPath)//configs
$(ProjectPath)/board/wujian100_open_evb/include
$(ProjectPath)/csi_core/include
$(ProjectPath)/csi_driver/include
$(ProjectPath)/csi_driver/wujian100_open/include
$(ProjectPath)/csi_kernel/include
$(ProjectPath)/csi_kernel/rhino/arch/include
$(ProjectPath)/csi_kernel/rhino/common
$(ProjectPath)/csi_kernel/rhino/core/include
$(ProjectPath)/csi_kernel/rhino/driver
$(ProjectPath)/csi_kernel/rhino/pwrmgmt
$(ProjectPath)/include
$(ProjectPath)/libs/include
$(ProjectPath)/libs/include/ringbuffer
$(ProjectPath)/libs/include/sys

In Assembler label we need also change the include path to be like following.
```
$(ProjectPath)
$(ProjectPath)//configs
```
In Linker label under link file dock, we must change that into our gcc_csky.ld file.
```
$(ProjectPath)/board/wujian100_open_evb/gcc_csky.ld
```
In User laber under Run user programm AFTER build/rebuild dock, we need to change that into our after_bd.sh
```
$(ProjectPath)/utilities/aft_build.sh
```
Click OK to end the configuration.
Build the project and finally we could see the Done message.

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This article might be updated in the future, please refer to the original site: https://shieldjy.github.io/post/FPGA-Development-with-WJ100-SoC-P3.html , to avoid misleading by false or out-dated information, and to have a better reading experience.

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