shieldjy

NeuroSim Part 1

Tue, 06 Apr 2021 10:00:06 +0000

Getting started

About This Project

NeuroSim+ is an integrated simulation framework for benchmarking synaptic devices and array architectures in terms of the system-level learning accuracy and hardware performance metrics[1]. Firstly introduced by Prof. Yumeng Shi at GaTech, it has now iterated to its third version MLP_NeuroSim_V3.0. More information could be referred from the links below.

related websites Laboratory for Emerging Devices and Circuits Chen,2017 NeuroSim

Running the Instance

As stated in its User Mannual

Thus, a brand new virtual Ubuntu 16.04 running in VMWare Workstation 15.0 is established to help this model running.

However, during last trial, my 16GB memory for that virtual machine was used up and caused a major breakdown. Then I found that I was unable to access the Ubuntu with graphic but only command lines. I assume it was because I shut down the virtual machine compulsively without following the VMWare protocol and caused some protection mechanism. **So, it is highly unrecommend to run this model with small memory and highly unrecommend to shut down the virtual machines causally.**

Anyway, I found Ubuntu 16.04 is unbearably old and extremely unfriendly. So I set up a brand new Ubuntu 20.04 LTS to run this instance. Noting that you should make sure the internet connection between the system and VMWare is all right since the installation process needs internet to install VM-Tool which enables the copy-paste between your Windows and Ubuntu as well as the full-screen feature. To ensure this connectivity, be aware that the ‘network connection’ should be set as ‘Customized’ and set it to ‘VMnet8(NAT Mode)’ as shown below.

Then press Ctrl+Alt+T to open the Terminal to do the common procedure for a brand new Ubuntu system

sudo apt-get update

sudo apt-get upgrade

sudo apt-get install build-essential

Afterwards, install git, gcc, and g++ with

sudo apt-get install git

sudo apt-get install gcc

sudo apt-get install g++

Then follow the steps shown on MLP_NeuroSim_V3.0

git clone https://github.com/neurosim/MLP_NeuroSim_V3.0.git

Open that folder and extract the file MNIST_data.zip to it’s current directory

cd MLP_NeuroSim_V3.0/

unzip MNIST_data.zip

Make the files

make

Following the instructions in the user guide provided in User Manual, the terminal should output the information below.

According to the User Manual, there are several params that could be adjusted. They are listed below. Please refer to Section 5.3 in User Manual to get further information about the param and its usage. Here is just a simple list of them.

Param	Value(s)	File
Device Type	RealDevice IdealDevice MeasuredDevice DIgitalNVM SRAM	main.cpp
Nonlinear Weight Update	NL_LTP NL_LTD	cell.cpp
Limited Precision	maxNumLevelLTP minNumLevelLTP	cell.cpp
Device-to-device weight update variation	sigmaDtoD	cell.cpp
Cycle-to-cycle weight update variation	sigmaCtoC	cell.cpp
Dynamic range	maxConductance minConductance	cell.cpp
Conductance variation	maxConductance minConductance	cell.cpp
Read noise	sigmaReadNoise	cell.cpp
Others	cmosAccess resistanceAccess FeFET gateCapFeFET NL nonIdenticalPulse VinitLTP VstepLTP VinitLTD VstepLTD PWinitLTP PWstepLTP PWinitLTD PWstepLTD	cell.cpp

To give it a try, we just use the default values and default device (RealDevice).

make run

and see the outputs.

Can see the accuracy from the last (125) epoch is 69.95%.

Also, the output log is stored in the MLP-NeuroSim_V3.0 Directory as a txt file for the reference.

FPGA Development with wujian100 SoC - Part Ten: Add On-Board Buttons to SoC

Sat, 08 Aug 2020 19:00:06 +0000

Add On-Board Buttons to SoC

FPGA Development with wujian100 SoC

Part Ten: Add On-Board Buttons to SoC

Author: 加一(Jiayi)

Something to say

Recently I participate a contest named Integrate Circuit Innovation Contest which requires me to use WJ100 developed by Ali Inc. team t-head and a FPGA develop board with Xlinx XC7A200TR3B Core. It’s not my first time to cope with FPGA but still, I find it difficult to interpret Verilog Code and make the FPGA works. Luckily, with the help of WJ100 Sdk and CDK(C-sky Develop Kit) which developed by Ali Inc. we could jump the Verilog and long waiting synthesizing part directly to use the pre-setted circuit and easy writing C to develop.

About WJ100

According to the official sites of t-head Inc., WJ100 is a low cost and high power efficiency SoC, which barely means that it could be easily deployed on any chips and consumes lower power.

However, as I talked before, it is a open source project and as I believed, the real function of this SoC is to simplify the use of FPGA and to offer the developer a brand new way to develop: integrate Soc and FPGA to deal with some projects which require both power efficiency and fast steady frequency.

related websites t-head

How to use WJ100 SoC

This tutorial is for those who utilize vivado to generate bitstream file and CDK to develop your own projects on Windows.

For Part 1 Bitsream Generation please refer to Part_1_Bitstream_Generation.
For Part 2 CDK Toolkit and wujian100 SDK please refer to Part_2_CDK_Toolkit&Wujian100_SDK.
For Part 3 Start a New Project on CDK please refer to Part_3_Start_a_New_Project_on_CDK
For Part 4 Hello World please refer to Part4_Hello_World
For Part 5 GPIO please refer to Part5_GPIO
For Part 6 UART please refer to Part6_UART
For Part 7 TIMER please refer to Part7_TIMER
For Part 8 Interrupt please refer to Part8_VIC
For Part 9 Working on Bugs please refer to Part9_BUGs

Part 10 Add On-Board Buttons to SoC

According to the official file, there are four keys that could be defined seperately by the user. And only one of them is pre-defined in SoC(K3 which is PB4 in wujian100). The table is shown in table 1.

table 1 user defined key signal connection with FPGA User defined key|Signal Name|FPGA U1|Name in Soc K3|KEY1|U1.AB7|PB4_XX_XX_XX_UART3TX K4|KEY2|U1.Y8| K5|KEY3|U1.AB6| K6|KEY4|U1.V8|

As shown above, I have searched in wujian100_open project for specific word and have found in XC7A200T3B.xdc file which defines the pins of FPGA and what it reflects inner the SoC. Then I found definitions related to user keys are commented by the officials shown as code below.

    #===========================================
    # USER KEYs:
    #===========================================
    #set_property PACKAGE_PIN AB7   [get_ports ];	#k3
    #set_property PACKAGE_PIN Y8    [get_ports {gpio0_port[2]}];	#k4
    #set_property PACKAGE_PIN AB6   [get_ports {gpio0_port[3]}];	#k5
    #set_property PACKAGE_PIN V8    [get_ports {gpio0_port[4]}];	#k6

As we could see, the Port on FPGA is not mapped correctly to where we expect it would be. Hence, I changed the mapping ralation and got the codes below.

    #===========================================
    # USER KEYs:
    #===========================================
    #set_property PACKAGE_PIN AB7   [get_ports ];	#k3
    set_property PACKAGE_PIN Y8    [get_ports PAD_GPIO_29];	#k4
    set_property PACKAGE_PIN AB6   [get_ports PAD_GPIO_30];	#k5
    set_property PACKAGE_PIN V8    [get_ports PAD_GPIO_31];	#k6

After changing the mapping relationship of GPIO in SoC, there might be conflict between newly established pin and already existed ones. So, we need to comment those codes below to prevent errors.

    #===========================================
    # YOC SOCKET 2
    #===========================================
    #set_property PACKAGE_PIN U20     [get_ports PAD_GPIO_29]
    #set_property PACKAGE_PIN AB20    [get_ports PAD_GPIO_30]
    #set_property PACKAGE_PIN T20     [get_ports PAD_GPIO_31]

Then follow the steps in Part_1_Bitstream_Generation to generate a bitstream file and test if it works in wujian100.

FPGA Development with wujian100 SoC - Part Nine: Working on Bugs

Sun, 17 May 2020 07:44:25 +0000

Bug issue.

FPGA Development with wujian100 SoC

Part Nine: Working on Bugs

Author: 加一(Jiayi)

Something to say

About WJ100

According to the official sites of t-head Inc., WJ100 is a low cost and high power efficiency SoC, which barely means that it could be easily deployed on any chips and consumes lower power.

related websites t-head

How to use WJ100 SoC

This tutorial is for those who utilize vivado to generate bitstream file and CDK to develop your own projects on Windows.

For Part 1 Bitsream Generation please refer to Part_1_Bitstream_Generation.
For Part 2 CDK Toolkit and wujian100 SDK please refer to Part_2_CDK_Toolkit&Wujian100_SDK.
For Part 3 Start a New Project on CDK please refer to Part_3_Start_a_New_Project_on_CDK
For Part 4 Hello World please refer to Part4_Hello_World
For Part 5 GPIO please refer to Part5_GPIO
For Part 6 UART please refer to Part6_UART
For Part 7 TIMER please refer to Part7_TIMER
For Part 8 Interrupt please refer to Part8_VIC

Part 9 Bugs Issue

001 return problem

category	compiler bug
solved	NO
confirmed	YES
Discription	As shown in code block, delay_flag will become 0 when interrupt is triggered. However, after I tested several times, whatever the judgment condition is, i.e. `delay_flag <= 0` or `delay_flag != 1`, the function just seems to stuck with `while`. And further experiments conducted by adding a `printf` function in the `if` statement shows that the judgement would work so that the only bug is about `return` statement. More informantion is digged when I see what is wrong with the assemble language and I found there is no `jmp` to return to the function where it originally is but a `jmp` statement to return to something implements the infinite `while` loop. Further experiments showns that this problem occurs when there are more than 3 times of loop in `while` and then it will enter some infinite loop.

    while(1){
        if (delay_flag == 0) {
            return 0;
        }
    }

Feel free to comment for your opinions or bugs you have found, I will continuously update this bug issue article.

SoC on FPGA - Part One: Overview

Wed, 22 Apr 2020 01:00:25 +0000

General introduction to FPGA and SoC.

A decent song for you.

FPGA, short for Field-Programmable Gate Array, and SoC, short for System on Chip are recently always brought to the media for its widely appilication. This article will illustrate briefly about what is SoC and what is FPGA.

System on Chip (SoC)

Different from Central Process Unit (CPU) or Graphic Process Unit (GPU), SoC is a type of core that contains everything a programmer would need to programme on it. What does this mean? Take Jack, a programmer as example. Jack want to assemble a computer. What does he need? An Intel Core® i9, Titan® X Graphic Card, Samsung® DDR4 Memory and EVO® 970 Solid State Drive. Also, he will need a motherboard to supply power and cooling CPU, GPU and other stuffs. Also a AC-DC converter is required. After that, he will need to install an operating system, i.e. Ubuntu or Windows on the machine. To programme on the computer, the programming environment is also required. After all that, he could finally run some programs on this newly built computer.

What about Bob, a SoC engineer? He would just need to buy an Arduino and a AC-DC converter for power supply.

What SoC different from CPU is clear, that SoC is actually a fully prepared system for anyone to use, it contains Algrithom and Logic Unit(ALU) working as CPU, Static Random-Access Memory(SRAM), Clock Source, Flash, Power Control Unit(PWC), etc. Engineer could directly write programmes into its Flash and it will read programme from it to Electrically-Erasable Programmable Read-Only Memory (EEPROM) then operate automatically. Because all we need to programme are in the SoC the tiny little chip. Figure 1 Arduino Uno Structure

Field-Programmable Gate Array (FPGA)

FPGA is quite different from what we have talked above, it is a totally “Free” stuff. It is a chip contains millions of gates. And what is gate? Gate is refered to Logic Gate, i.e. XOR(exclusive OR) gate and AND gate. With the basic logic gates, we could make thousands of arrays and create the digital devices in the Text Book of Digital Circuits. For example, a simple D-Flip Flop(DFF) unit is implemented by 4 NAND gate and one Inverter. Furthermore, a shift register could be implemented by several DFF. Figure 2 D-Flip Flop From electronic Hub

Since stuffs in a SoC are all digital except for AC-DC converter, they could be implemented by the FPGA and thus the FPGA could be used as a simple SoC. That is what FPGA is always used for, the early stage verifidication of ASIC.

Dynamic Random Access Memory

Wed, 15 Apr 2020 01:00:25 +0000

Research for DRAM.

1. What is DRAM

Dynamic random-access memory (DRAM) is a type of random access semiconductor memory that stores each bit of data in a memory cell consisting of a tiny capacitor and a transistor, both typically based on metal-oxide-semiconductor (MOS) technology.wikipedia

2. Structure of DRAM Cells

Figure 2.1 DRAM Cell Structure

From figure 2.1, as we could see, DRAM is actually a 1T1C(one transistor and one capacitor) structure. Writing process is accomplished by selecting bit line 1 and word line 2 thus pull up/down the voltage of capacitor 4. Firstly, data is stored by applying high voltage to both word line 2 and bit line 1. And then data is stored by applying a low voltage to the word line 2 and trapping the charge on the storage capacitor. Subsequently, the data is accessed by applying a high voltage to the wordline to make FET work in depletion mode, conduction bitline and capacitor, so that the voltage on the bit line 1 could be sensed. Then Word line or Bit line is turned to be Low Voltage Level to config next cell so that FET works in cut off mode and thus the voltage level is stored in capacitor 4. When the data is read, apply a high voltage on word line 2 and thus the charges in capacitor 4 is released and could be sensed in bit line 2.

However, this memory cell structure is volatile for two reason. For one, the voltage level of capacitor is hold due to its capacity of charges, but the charges will leak as time passed by. This process is basically due to the current leakage. And there is an important term names retention time. The retention time can be defined as the duration until the stored signal can be read out. There are several leakage current mechanisms, by which the stored signal disappears [11]. Including 1) junction leakage current from the storage node, 2) subthreshold leakage current of the transfer transistor, 3) capacitor dielectric leakage current, 4) gate induced drain leakage (GIDL) current at the storage node,5) gate dielectric leakage current, and 6) isolation leakage current between the neighboring cells. Study shows, the major leakage paths in a DRAM cell are reverse junction leakage from the storage node and gate induced drain leakage (GIDL) current [1]. For two, the reading process, the process we have discussed before, is destructive to the charge stored in the capacitor, which stands for the data. And this is due to its 1T1C structure.

Hence, Dynamic Random Access memory, although cheap to manufacture (in contrast to early stage solid states hard drive), fast read - write process and almost unlimited read-write cycles, has a fatal problem. It’s volatile feature. But nowadays there are problems with solid state memories and also with traditional DRAM. So there are quite a few researches that deal with the novel structure of DRAM and novel FET(Field Effect Transistors).

3. Latest researches on DRAM

Volatile

Volatile memory means the storage device will lose its data once the power is cut off.

Float Body Cell (FBC) Structure for 1T-DRAM

Although the principle of 1T1C DRAM is relatively simple, the capacitor in it is not that simple, for it requires a relatively large capacity of charge in its scale (around 30 fF/cell). Anyone who has some knowledge about capacitor should aware that Farad is not a small unit, 10mF capacitor could be called as “Super Capacitor” and is huge for a normal sized PCB.

Figure 3.1 a 10 Farad Super Capacitor(in contrast to a quart coin)

It is not difficult to imagine how large it is for a 30fF Cap in a DRAM cell. To deal with this issue, some reseachers[2]-[10] create a 1T structure, or floating-body cell (FBC) for DRAM. The FBC structure is shown in Figure 3.2. It operates as follows: When excess holes exist in the floating-body and Vth lowers, the cell state can be regarded as “1”. On the other hand, when excess holes are swept out of the floating-body by a forward bias on the body–drain junction and Vth becomes higher, the cell state can be regarded as “0”. The drain-current difference between “1” and “0” states can be sensed in the linear current region so as not to change the number of holes by the II current[2], which is an impact-ionization current used in wrting process.

Figure 3.2 1T Structure of DRAM

In contrast to 1T1C DRAM cells, the writing process with GIDL current consume lower by four orders of magnitude of power and a write speed within several nanoseconds. According to its data, Power consumption for writing “1” could be as low as $2.4 \times 10^-8$ Watt [2]. Furthermore, the reading process is non-destructive. However, this novel method is not widely taken for it has fatal weakness: its writing process is heavily relied on II current and 1 and 0 states detected by current. This is not what we truly like in an operating device. Since millions of cells could produce a huge current what requires the impedance of the whole device must be extradentary low, which is unachievable. Moreover, threads of devices are not designed to drain current for it is designed with a high pull up resistor to increase its impedance so as to increase its capability of voltage detection. The 1T DRAM could not be compatible with most common device.

Non-Volatile

Non-volatile memory (NVM) means the storage device will not lose its data after a relatively long time of cutting off. The time for how long its data could remain is called retention time and is an important measurement for non-volatile memory.

Non-volatile memory has been widely used in SRAM which is a high speed but large cell structure and Flash which is low speed but high density.

Figure 3.3 Memory taxonomy from the 2013 ITRS Emerging Research Devices (ERD) chapter[12]

Typically, there are several types of Non-Volatile memory cells, shown as right part in Figure 3.3. Categorized by cell technology, for instance, phase change memory, know as PCM, spin-transfer-torque random access memory, known as STTRAM, resistive random access memory, known as RRAM and ferroelectric field- effective-transistor memory, known as FeFET Memory.

Categorized by material used in the cell, there are inorganic and organic way. Among those, inorganic non-volatile memories have now been put into industrial manufacture, for instance Ferroelectric Random Access Memory (FRAM).

However, in this article, NVM categorized by organic and in-organic way will be discussed.

Inorganic Non-Volatile Memory Cells

Organic Non-Volatile Memory Cells

Reference

[1] u, J. and K. Aflatooni (2006). Leakage Current in DRAM Memory Cell. 2006 16th Biennial University/Government/Industry Microelectronics Symposium.

[2] Yoshida, E. and T. Tanaka (2006). “A capacitorless 1T-DRAM technology using gate-induced drain-leakage (GIDL) current for low-power and high-speed embedded memory.” IEEE TRANSACTIONS ON ELECTRON DEVICES 53(4): 692-697. Sasaki, N., et al. (1978). Charge pumping SOS-MOS transistor memory. 1978 International Electron Devices Meeting, IEEE.

[3] Tack, M. R., et al. (1990). “The multistable charge-controlled memory effect in SOI MOS transistors at low temperatures.” IEEE TRANSACTIONS ON ELECTRON DEVICES 37(5): 1373-1382.

[4] Wann, H.-J. and C. Hu (1993). A capacitorless DRAM cell on SOI substrate. Proceedings of IEEE International Electron Devices Meeting, IEEE.

[5] Okhonin, S., et al. (2001). A SOI capacitor-less 1T-DRAM concept. 2001 IEEE International SOI Conference. Proceedings (Cat. No. 01CH37207), IEEE.

[6] Fazan, P., et al. (2002). Capacitor-less 1-transistor DRAM. 2002 IEEE international SOI conference (Williamsburg VA, 7-10 October 2002).

[7] Ohsawa, T., et al. (2002). “Memory design using a one-transistor gain cell on SOI.” IEEE Journal of Solid-State Circuits 37(11): 1510-1522.

[8] Inoh, K., et al. (2003). FBC (floating body cell) for embedded DRAM on SOI. 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No. 03CH37407), IEEE.

[9] Yoshida, E. and T. Tanaka (2003). A design of a capacitorless 1T-DRAM cell using gate-induced drain leakage (GIDL) current for low-power and high-speed embedded memory. IEEE International Electron Devices Meeting 2003, IEEE.

[10] Shino, T., et al. (2004). Highly scalable FBC (floating body cell) with 25nm BOX structure for embedded DRAM applications. Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., IEEE.

[11]Hamamoto, T., et al. (1998). “On the retention time distribution of dynamic random access memory (DRAM).” IEEE TRANSACTIONS ON ELECTRON DEVICES 45(6): 1300-1309.

[12]ITRS Emerging Research Devices Chapter, 2013.

FPGA Development with wujian100 SoC - Part EIGHT: Interrupt(VIC)

Mon, 13 Apr 2020 01:00:25 +0000

Use Interrupt in wujian100 SoC.

FPGA Development with wujian100 SoC

Part EIGHT: Interrupt (VIC)

Author: 加一(Jiayi)

Something to say

About WJ100

According to the official sites of t-head Inc., WJ100 is a low cost and high power efficiency SoC, which barely means that it could be easily deployed on any chips and consumes lower power.

related websites t-head

How to use WJ100 SoC

For Part 1 Bitsream Generation please refer to Part_1_Bitstream_Generation.
For Part 2 CDK Toolkit and wujian100 SDK please refer to Part_2_CDK_Toolkit&Wujian100_SDK.
For Part 3 Start a New Project on CDK please refer to Part_3_Start_a_New_Project_on_CDK
For Part 4 Hello World please refer to Part4_Hello_World
For Part 5 GPIO please refer to Part5_GPIO
For Part 6 UART please refer to Part6_UART
For Part 7 TIMER please refer to Part7_TIMER
For Part 8 Interrupt please refer to Part8_VIC

Part 8 Interrupt

1 What is Interrupt

For more information about interrupt, please refer to wikipedia

2 What is VIC

VIC stands for vector interrupt controller, which is actually a pointer points to the interrupt vector table that associates a list of interrupt handlers with a list of interrupt requests in a table of interrupt vectors. Thus this controller controls the sequece of interrupt to make sure the program runs well.

3 How does interrupt work

Normally, interrupt is triggered by interrupt handler. Interrupt handler could been categrized by several methods, i.e. internally or externally, level triggerd or edge triggered for external trigger. External trigger is always related to GPIO or UART, and Internal trigger is always related with timer, watch dog(used to prevent some error), etc.

The interrupt handler will send a request to VIC in CPU, and CPU will arrange the request according to interrupt vector table (IVT). Once the interrupt has been operated by CPU, the normal programme routine (what are in main function) is hanged and the interrupt callback function which pre-stored in the IVT will come to work.

4 What do we get in wujian100

    User_Software_IRQn              =   0,      /* User software interrupt */
    Supervisor_Software_IRQn        =   1,      /* Supervisor software interrupt */
    Machine_Software_IRQn           =   3,      /* Machine software interrupt */
    User_Timer_IRQn                 =   4,      /* User timer interrupt */
    Supervisor_Timer_IRQn           =   5,      /* Supervisor timer interrupt */
    CORET_IRQn                      =   7,      /* core Timer Interrupt */
    GPIO0_IRQn                      =   16,     /* uart Interrupt */
    TIM0_IRQn                       =   17,     /* timer0 Interrupt */
    TIM1_IRQn                       =   18,     /* timer1 Interrupt */
    TIM2_IRQn                       =   19,     /* timer2 Interrupt */
    TIM3_IRQn                       =   20,     /* timer3 Interrupt */
    TIM4_IRQn                       =   21,     /* timer4 Interrupt */
    TIM5_IRQn                       =   22,     /* timer5 Interrupt */
    TIM6_IRQn                       =   23,     /* timer6 Interrupt */
    TIM7_IRQn                       =   24,     /* timer7 Interrupt */
    PWM_IRQn                        =   25,     /* pwm Interrupt */
    RTC_IRQn                        =   26,     /* rtc Interrupt */
    WDT_IRQn                        =   27,     /* wdt Interrupt */
    USI0_IRQn                       =   28,     /* usi0 Interrupt */
    USI1_IRQn                       =   29,     /* usi1 Interrupt */
    USI2_IRQn                       =   30,     /* usi2 Interrupt */
    PMU_IRQn                        =   31,     /* pmu Interrupt */
    DMAC0_IRQn                      =   32,     /* dmac0 Interrupt */
    TIM8_IRQn                       =   33,     /* timer8 Interrupt */
    TIM9_IRQn                       =   34,     /* timer9 Interrupt */
    TIM10_IRQn                       =  35,     /* timer10 Interrupt */
    TIM11_IRQn                       =  36,     /* timer11 Interrupt */
    TIM12_IRQn                       =  37,     /* timer12 Interrupt */
    TIM13_IRQn                       =  38,     /* timer13 Interrupt */
    TIM14_IRQn                       =  39,     /* timer14 Interrupt */
    TIM15_IRQn                       =  40,     /* timer15 Interrupt */

According to enumerate type IRQn in soc.h, there are basically 10 types of interrupt, i.e., software interrupt, timer, gpio, pwm(palse width modulation), rtc(real time clock), coret(core timer), wdt(watchdog timer), usi(universal serial interface), dmac(direct memory access), pmu(power management unit).

To dig more, we could find functions that set VIC in core_rv32.h.

/**
/**
  \ingroup  CSI_Core_FunctionInterface
  \defgroup CSI_Core_VICFunctions VIC Functions
  \brief    Functions that manage interrupts and exceptions via the VIC.
  @{
 */

/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    5UL)      )
#define _IP2_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )

/**
  \brief   Enable External Interrupt
  \details Enable a device-specific interrupt in the VIC interrupt controller.
  \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void csi_vic_enable_irq(int32_t IRQn)
{
    CLIC->INTIE[IRQn] |= CLIC_INTIE_IE_Msk;
}

/**
  \brief   Disable External Interrupt
  \details Disable a device-specific interrupt in the VIC interrupt controller.
  \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void csi_vic_disable_irq(int32_t IRQn)
{
    CLIC->INTIE[IRQn] &= ~CLIC_INTIE_IE_Msk;
}

/**
  \brief   Enable External Secure Interrupt
  \details Enable a secure device-specific interrupt in the VIC interrupt controller.
  \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void csi_vic_enable_sirq(int32_t IRQn)
{
    CLIC->INTIE[IRQn] |= (CLIC_INTIE_IE_Msk | CLIC_INTIE_T_Msk);
}

/**
  \brief   Disable External Secure Interrupt
  \details Disable a secure device-specific interrupt in the VIC interrupt controller.
  \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void csi_vic_disable_sirq(int32_t IRQn)
{
    CLIC->INTIE[IRQn] &= ~(CLIC_INTIE_IE_Msk | CLIC_INTIE_T_Msk);
}

/**
  \brief   Check Interrupt is Enabled or not
  \details Read the enabled register in the VIC and returns the pending bit for the specified interrupt.
  \param [in]      IRQn  Interrupt number.
  \return             0  Interrupt status is not enabled.
  \return             1  Interrupt status is enabled.
 */
__STATIC_INLINE uint32_t csi_vic_get_enabled_irq(int32_t IRQn)
{
    return (uint32_t)(CLIC->INTIE[IRQn] & CLIC_INTIE_IE_Msk);
}

/**
  \brief   Check Interrupt is Pending or not
  \details Read the pending register in the VIC and returns the pending bit for the specified interrupt.
  \param [in]      IRQn  Interrupt number.
  \return             0  Interrupt status is not pending.
  \return             1  Interrupt status is pending.
 */
__STATIC_INLINE uint32_t csi_vic_get_pending_irq(int32_t IRQn)
{
    return (uint32_t)(CLIC->INTIP[IRQn] & CLIC_INTIP_IP_Msk);
}

/**
  \brief   Set Pending Interrupt
  \details Set the pending bit of an external interrupt.
  \param [in]      IRQn  Interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void csi_vic_set_pending_irq(int32_t IRQn)
{
    CLIC->INTIP[IRQn] |= CLIC_INTIP_IP_Msk;
}

/**
  \brief   Clear Pending Interrupt
  \details Clear the pending bit of an external interrupt.
  \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void csi_vic_clear_pending_irq(int32_t IRQn)
{
    CLIC->INTIP[IRQn] &= ~CLIC_INTIP_IP_Msk;
}

/**
  \brief   Set Interrupt Priority
  \details Set the priority of an interrupt.
  \note    The priority cannot be set for every core interrupt.
  \param [in]      IRQn  Interrupt number.
  \param [in]  priority  Priority to set.
 */
__STATIC_INLINE void csi_vic_set_prio(int32_t IRQn, uint32_t priority)
{
    CLIC->INTCFG[IRQn] = (CLIC->INTCFG[IRQn] & (~CLIC_INTCFG_PRIO_Msk)) | (priority << CLIC_INTCFG_PRIO_Pos);
}

/**
  \brief   Get Interrupt Priority
  \details Read the priority of an interrupt.
           The interrupt number can be positive to specify an external (device specific) interrupt,
           or negative to specify an internal (core) interrupt.
  \param [in]   IRQn  Interrupt number.
  \return             Interrupt Priority.
                      Value is aligned automatically to the implemented priority bits of the microcontroller.
 */
__STATIC_INLINE uint32_t csi_vic_get_prio(int32_t IRQn)
{
    return CLIC->INTCFG[IRQn] >> CLIC_INTCFG_PRIO_Pos;
}

/**
  \brief   Set interrupt handler
  \details Set the interrupt handler according to the interrupt num, the handler will be filled in irq vectors.
  \param [in]      IRQn  Interrupt number.
  \param [in]   handler  Interrupt handler.
 */
__STATIC_INLINE void csi_vic_set_vector(int32_t IRQn, uint32_t handler)
{
    if (IRQn >= 0 && IRQn < 1024) {
        uint32_t *vectors = (uint32_t *)__get_MTVT();
        vectors[32 + IRQn] = handler;
    }
}

/**
  \brief   Get interrupt handler
  \details Get the address of interrupt handler function.
  \param [in]      IRQn  Interrupt number.
 */
__STATIC_INLINE uint32_t csi_vic_get_vector(int32_t IRQn)
{
    if (IRQn >= 0 && IRQn < 1024) {
        uint32_t *vectors = (uint32_t *)__get_MTVT();
        return (uint32_t)vectors[32 + IRQn];
    }

    return 0;
}

Fortunately, most of them are functions called by the system. Hence there are quite few functions we might use.

For example, we might only use csi_vic_set_prio in the interrupt configuration part.

/**
  \brief   Set Interrupt Priority
  \details Set the priority of an interrupt.
  \note    The priority cannot be set for every core interrupt.
  \param [in]      IRQn  Interrupt number.
  \param [in]  priority  Priority to set.
 */
__STATIC_INLINE void csi_vic_set_prio(int32_t IRQn, uint32_t priority)
{
    CLIC->INTCFG[IRQn] = (CLIC->INTCFG[IRQn] & (~CLIC_INTCFG_PRIO_Msk)) | (priority << CLIC_INTCFG_PRIO_Pos);
}

However, IRQ interrupt priority is `strongly advised` to prevent some sequence error, since t-head Inc. does not offer us official paper about default IRQ sequence.

5 How to use VIC

Luckily, although VIC is complicated inside the SoC, the usage is quite simple. All we need to do is simply add a line to set priority after configuring the interrupt, take timer as example.

/*initialize timer handler*/
timer_handle = csi_timer_initialize(timer_num, timer_event_cb_fun);
/*config timer*/
ret = csi_timer_config(timer_handle, TIMER_MODE_RELOAD);
/*config priority*/
csi_vic_set_prio(TIMER0_IRQn, LO_PRIO);
/*set timer timeout*/
csi_timer_set_timeout(timer_handle, 1000 * timeout_ms);

Note the first param in csi_vic_set_prio must be one of the enumerate types in IRQn_type above and should be the interrupt that you would like to configure.

FPGA Development with wujian100 SoC - Part SEVEN: TIMER

Thu, 09 Apr 2020 01:00:25 +0000

Use Timer in wujian100 SoC.

FPGA Development with wujian100 SoC

Part SEVEN: TIMER

Author: 加一(Jiayi)

Something to say

About WJ100

According to the official sites of t-head Inc., WJ100 is a low cost and high power efficiency SoC, which barely means that it could be easily deployed on any chips and consumes lower power.

related websites t-head

How to use WJ100 SoC

This tutorial is for those who utilize vivado to generate bitstream file and CDK to develop your own projects on Windows.

For Part 1 Bitsream Generation please refer to Part_1_Bitstream_Generation.
For Part 2 CDK Toolkit and wujian100 SDK please refer to Part_2_CDK_Toolkit&Wujian100_SDK.
For Part 3 Start a New Project on CDK please refer to Part_3_Start_a_New_Project_on_CDK
For Part 4 Hello World please refer to Part4_Hello_World
For Part 5 GPIO please refer to Part5_GPIO
For Part 6 UART please refer to Part6_UART
For Part 7 TIMER please refer to Part7_TIMER
For Part 8 Interrupt please refer to Part8_VIC

Part 7 TIMER

1 What is Timer

Timer is a count up counter in SoC. There are normally several opration modes for timer, for example, auto-reload mode, counter mode, manual reload mode, etc. Interrupt is normally used when using auto-reload mode timer for controlling dc motor or any device requires periodical responds.

In wujian100 SoC, there are 16 channels/timers which I am not sure about since the official does not offer any docs. However, there are two modes, i.e. reload mode and freerunning mode which again i am not sure what freerunning could be used for.

2 Let us see what we have got in library

Timer is quite a simple module to use in wujian100 and hence it does not offer us many advanced options. Here is library for timer which could be found in .\csi_driver\include\drv_timer.h.

/**
  \brief       Initialize TIMER Interface. 1. Initializes the resources needed for the TIMER interface 2.registers event callback function
  \param[in]   idx  timer index
  \param[in]   cb_event  event call back function \ref timer_event_cb_t
  \param[in]   cb_arg    arguments of cb_event
  \return      pointer to timer instance
*/
timer_handle_t csi_timer_initialize(int32_t idx, timer_event_cb_t cb_event);

/**
  \brief       De-initialize TIMER Interface. stops operation and releases the software resources used by the interface
  \param[in]   handle timer handle to operate.
  \return      error code
*/
int32_t csi_timer_uninitialize(timer_handle_t handle);

/**
  \brief       control timer power.
  \param[in]   handle  timer handle to operate.
  \param[in]   state   power state.\ref csi_power_stat_e.
  \return      error code
*/
int32_t csi_timer_power_control(timer_handle_t handle, csi_power_stat_e state);

/**
  \brief       config timer mode.
  \param[in]   handle timer handle to operate.
  \param[in]   mode      \ref timer_mode_e
  \return      error code
*/
int32_t csi_timer_config(timer_handle_t handle, timer_mode_e mode);

/**
  \brief       Set timeout just for the reload mode.
  \param[in]   handle timer handle to operate.
  \param[in]   timeout the timeout value in microseconds(us).
  \return      error code
*/
int32_t csi_timer_set_timeout(timer_handle_t handle, uint32_t timeout);

/**
  \brief       Start timer.
  \param[in]   handle timer handle to operate.
  \return      error code
*/
int32_t csi_timer_start(timer_handle_t handle);

/**
  \brief       Stop timer.
  \param[in]   handle timer handle to operate.
  \return      error code
*/
int32_t csi_timer_stop(timer_handle_t handle);

/**
  \brief       suspend timer.
  \param[in]   handle timer handle to operate.
  \return      error code
*/
int32_t csi_timer_suspend(timer_handle_t handle);

/**
  \brief       resume timer.
  \param[in]   handle timer handle to operate.
  \return      error code
*/
int32_t csi_timer_resume(timer_handle_t handle);

/**
  \brief       get timer current value
  \param[in]   handle timer handle to operate.
  \param[out]   value     timer current value
  \return      error code
*/
int32_t csi_timer_get_current_value(timer_handle_t handle, uint32_t *value);

/**
  \brief       Get TIMER status.
  \param[in]   handle timer handle to operate.
  \return      TIMER status \ref timer_status_t
*/
timer_status_t csi_timer_get_status(timer_handle_t handle);

/**
  \brief       get timer reload value
  \param[in]   handle timer handle to operate.
  \param[out]   value    timer reload value
  \return      error code
*/
int32_t csi_timer_get_load_value(timer_handle_t handle, uint32_t *value);

Be sure not to use function csi_timer_suspend since I found it actually an empty function and could only return error code.

/**
  \brief       suspend timer.
  \param[in]   instance  timer instance to operate.
  \return      error code
*/
int32_t csi_timer_suspend(timer_handle_t handle)
{
    TIMER_NULL_PARAM_CHK(handle);

    return ERR_TIMER(DRV_ERROR_UNSUPPORTED);
}

3 How to use these functions

Now we have reached to the high points of this article, the use of Timer in wujian100 SoC.

Initialize timer handler. timer_num is the timer you would like to use, i.e. 0 for timer0, 1 for timer1, etc. And just like what we did in UART part, we had better write a callback function to deal with timer interrupt event call back.
```
 timer_handle = csi_timer_initialize(timer_num, timer_event_cb_fun);
```

configure timer as anyway you would like it to be.

 csi_timer_config(timer_handle, TIMER_MODE_RELOAD);

or for freerunning mode

 csi_timer_config(timer_handle, TIMER_MODE_FREE_RUNNING);

set timeout only in reload mode, timeout is in microseconds, i.e. us
```
 csi_timer_set_timeout(timer_handle, timeout_us);
```
start timer and say BINGO (must*) !
```
 csi_timer_start(timer_handle);
```
Remember to put something in callback function. Otherwise you would see nothing is happening. And more intriging thing in CDK is that stop points does not work in call back function which make it difficult to debug interrupt which I will write about in next article.

Note* It does not really matter if you say bingo or not.

FPGA Development with wujian100 SoC - Part Six: UART

Wed, 08 Apr 2020 01:00:25 +0000

Send and receive text with UART in wujian100 SoC.

FPGA Development with wujian100 SoC

Part Six: UART

Author: 加一(Jiayi)

Something to say

About WJ100

According to the official sites of t-head Inc., WJ100 is a low cost and high power efficiency SoC, which barely means that it could be easily deployed on any chips and consumes lower power.

related websites t-head

How to use WJ100 SoC

This tutorial is for those who utilize vivado to generate bitstream file and CDK to develop your own projects on Windows.

For Part 1 Bitsream Generation please refer to Part_1_Bitstream_Generation.
For Part 2 CDK Toolkit and wujian100 SDK please refer to Part_2_CDK_Toolkit&Wujian100_SDK.
For Part 3 Start a New Project on CDK please refer to Part_3_Start_a_New_Project_on_CDK
For Part 4 Hello World please refer to Part4_Hello_World
For Part 5 GPIO please refer to Part5_GPIO
For Part 6 UART please refer to Part6_UART
For Part 7 TIMER please refer to Part7_TIMER
For Part 8 Interrupt please refer to Part8_VIC

Part 6 UART

1 What is UART

UART stands for universal asynchronous receiver-transmitter, however, wujian100 supports synchronous receiver and transmitter. It is more accurate to call it universal synchronous or asynchronous receiver-transmitter(USART). But we will follow UART since synchronous mode is quite useless unless you might want some high speed message or in other cases, we would prefer to use iic instead UART.

For more UART knowledge, please refer to wikipedia

2 Let us see what we have got in library

Open .\csi_driver\wujian100_open\include\drv_usi_usart.h, as we could see in the following external functions that we could call. They are expained quite elaborate by t-head Inc..

/**
  \brief       Initialize USART Interface. 1. Initializes the resources needed for the USART interface 2.registers event callback function
  \param[in]   idx usart index
  \param[in]   cb_event  event call back function \ref usart_event_cb_t
  \return      return usart handle if success
*/
usart_handle_t drv_usi_usart_initialize(int32_t idx, usart_event_cb_t cb_event);

/**
  \brief       De-initialize USART Interface. stops operation and releases the software resources used by the interface
  \param[in]   handle  usart handle to operate.
  \return      error code
*/
int32_t drv_usi_usart_uninitialize(usart_handle_t handle);
/**
  \brief       Get driver capabilities.
  \param[in]   idx usart index
  \return      \ref usart_capabilities_t
*/
usart_capabilities_t drv_usi_usart_get_capabilities(int32_t idx);

/**
  \brief       config usart mode.
  \param[in]   handle  usart handle to operate.
  \param[in]   baud      baud rate.
  \param[in]   mode      \ref usart_mode_e .
  \param[in]   parity    \ref usart_parity_e .
  \param[in]   stopbits  \ref usart_stop_bits_e .
  \param[in]   bits      \ref usart_data_bits_e .
  \return      error code
*/
int32_t drv_usi_usart_config(usart_handle_t handle,
                             uint32_t baud,
                             usart_mode_e mode,
                             usart_parity_e parity,
                             usart_stop_bits_e stopbits,
                             usart_data_bits_e bits);


/**
  \brief       Start sending data to USART transmitter,(received data is ignored).
               This function is non-blocking,\ref usart_event_e is signaled when operation completes or error happens.
               \ref drv_usi_usart_get_status can get operation status.
  \param[in]   handle  usart handle to operate.
  \param[in]   data  Pointer to buffer with data to send to USART transmitter. data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits
  \param[in]   num   Number of data items to send
  \return      error code
*/
int32_t drv_usi_usart_send(usart_handle_t handle, const void *data, uint32_t num);

/**
  \brief       Abort Send data to USART transmitter
  \param[in]   handle  usart handle to operate.
  \return      error code
*/
int32_t drv_usi_usart_abort_send(usart_handle_t handle);

/**
  \brief       Start receiving data from USART receiver. \n
               This function is non-blocking,\ref usart_event_e is signaled when operation completes or error happens.
               \ref drv_usi_usart_get_status can get operation status.
  \param[in]   handle  usart handle to operate.
  \param[out]  data  Pointer to buffer for data to receive from USART receiver.data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits
  \param[in]   num   Number of data items to receive
  \return      error code
*/
int32_t drv_usi_usart_receive(usart_handle_t handle, void *data, uint32_t num);

/**
  \brief       query data from UART receiver FIFO.
  \param[in]   handle  usart handle to operate.
  \param[out]  data  Pointer to buffer for data to receive from UART receiver
  \param[in]   num   Number of data items to receive
  \return      fifo data num to receive
*/
int32_t drv_usi_usart_receive_query(usart_handle_t handle, void *data, uint32_t num);

/**
  \brief       Abort Receive data from USART receiver
  \param[in]   handle  usart handle to operate.
  \return      error code
*/
int32_t drv_usi_usart_abort_receive(usart_handle_t handle);

/**
  \brief       Start synchronously sends data to the USART transmitter and receives data from the USART receiver. used in synchronous mode
               This function is non-blocking,\ref usart_event_e is signaled when operation completes or error happens.
               \ref drv_usi_usart_get_status can get operation status.
  \param[in]   handle  usart handle to operate.
  \param[in]   data_out  Pointer to buffer with data to send to USART transmitter.data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits
  \param[out]  data_in   Pointer to buffer for data to receive from USART receiver.data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits
  \param[in]   num       Number of data items to transfer
  \return      error code
*/
int32_t drv_usi_usart_transfer(usart_handle_t handle, const void *data_out, void *data_in, uint32_t num);

/**
  \brief       abort sending/receiving data to/from USART transmitter/receiver.
  \param[in]   handle  usart handle to operate.
  \return      error code
*/
int32_t drv_usi_usart_abort_transfer(usart_handle_t handle);

/**
  \brief       Get USART status.
  \param[in]   handle  usart handle to operate.
  \return      USART status \ref usart_status_t
*/
usart_status_t drv_usi_usart_get_status(usart_handle_t handle);

/**
  \brief       flush receive/send data.
  \param[in]   handle usart handle to operate.
  \param[in]   type \ref usart_flush_type_e .
  \return      error code
*/
int32_t drv_usi_usart_flush(usart_handle_t handle, usart_flush_type_e type);

/**
  \brief       set interrupt mode.
  \param[in]   handle usart handle to operate.
  \param[in]   type \ref usart_intr_type_e.
  \param[in]   flag 0-OFF, 1-ON.
  \return      error code
*/
int32_t drv_usi_usart_set_interrupt(usart_handle_t handle, usart_intr_type_e type, int32_t flag);

/**
  \brief       set the baud rate of usart.
  \param[in]   baud  usart base to operate.
  \param[in]   baudrate baud rate
  \return      error code
*/
int32_t drv_usi_usart_config_baudrate(usart_handle_t handle, uint32_t baud);

/**
  \brief       config usart mode.
  \param[in]   handle  usart handle to operate.
  \param[in]   mode    \ref usart_mode_e
  \return      error code
*/
int32_t drv_usi_usart_config_mode(usart_handle_t handle, usart_mode_e mode);

/**
  \brief       config usart parity.
  \param[in]   handle  usart handle to operate.
  \param[in]   parity    \ref usart_parity_e
  \return      error code
*/
int32_t drv_usi_usart_config_parity(usart_handle_t handle, usart_parity_e parity);

/**
  \brief       config usart stop bit number.
  \param[in]   handle  usart handle to operate.
  \param[in]   stopbits  \ref usart_stop_bits_e
  \return      error code
*/
int32_t drv_usi_usart_config_stopbits(usart_handle_t handle, usart_stop_bits_e stopbit);

/**
  \brief       config usart data length.
  \param[in]   handle  usart handle to operate.
  \param[in]   databits      \ref usart_data_bits_e
  \return      error code
*/
int32_t drv_usi_usart_config_databits(usart_handle_t handle, usart_data_bits_e databits);

/**
  \brief       get character in query mode.
  \param[in]   handle  usart handle to operate.
  \param[out]  ch the pointer to the received character.
  \return      error code
*/
int32_t drv_usi_usart_getchar(usart_handle_t handle, uint8_t *ch);

/**
  \brief       transmit character in query mode.
  \param[in]   handle  usart handle to operate.
  \param[in]   ch  the input character
  \return      error code
*/
int32_t drv_usi_usart_putchar(usart_handle_t handle, uint8_t ch);

/**
  \brief       Get usart send data count.
  \param[in]   handle  usart handle to operate.
  \return      number of currently transmitted data bytes
*/
uint32_t drv_usi_usart_get_tx_count(usart_handle_t handle);

/**
  \brief       Get usart received data count.
  \param[in]   handle  usart handle to operate.
  \return      number of currently received data bytes
*/
uint32_t drv_usi_usart_get_rx_count(usart_handle_t handle);

/**
  \brief       control usart power.
  \param[in]   handle  usart handle to operate.
  \param[in]   state   power state.\ref drv_usi_power_stat_e.
  \return      error code
*/
int32_t drv_usi_usart_power_control(usart_handle_t handle, csi_power_stat_e state);

/**
  \brief       config usart flow control type.
  \param[in]   handle  usart handle to operate.
  \param[in]   flowctrl_type   flow control type.\ref usart_flowctrl_type_e.
  \return      error code
*/
int32_t drv_usi_usart_config_flowctrl(usart_handle_t handle,
                                      usart_flowctrl_type_e flowctrl_type);

/**
  \brief       config usart clock Polarity and Phase.
  \param[in]   handle  usart handle to operate.
  \param[in]   cpol    Clock Polarity.\ref usart_cpol_e.
  \param[in]   cpha    Clock Phase.\ref usart_cpha_e.
  \return      error code
*/
int32_t drv_usi_usart_config_clock(usart_handle_t handle, usart_cpol_e cpol, usart_cpha_e cpha);

/**
  \brief       control the transmitter.
  \param[in]   handle  usart handle to operate.
  \param[in]   enable  1 - enable the transmitter. 0 - disable the transmitter
  \return      error code
*/
int32_t drv_usi_usart_control_tx(usart_handle_t handle, uint32_t enable);

/**
  \brief       control the receiver.
  \param[in]   handle  usart handle to operate.
  \param[in]   enable  1 - enable the receiver. 0 - disable the receiver
  \return      error code
*/
int32_t drv_usi_usart_control_rx(usart_handle_t handle, uint32_t enable);

/**
  \brief       control the break.
  \param[in]   handle  usart handle to operate.
  \param[in]   enable  1- Enable continuous Break transmission,0 - disable continuous Break transmission
  \return      error code
*/
int32_t drv_usi_usart_control_break(usart_handle_t handle, uint32_t enable);

3 How to use these functions

Now we have reached to the high points of this article, the use of UART in wujian100 SoC.

Unitialize the UART in case pre-configuration has been done unpurposely.
```
 csi_usart_uninitialize(usart);
```

Initialize usart handler and make sure to create a global handler.

  usart = csi_usart_initialize(uart_idx, (usart_event_cb_t)usart_event_cb);
  g_usart_handle = usart;

Configure usart, in this case usart has been configured as asychronous mode without parity flag, with 115200 baud rate, one stop bits and eight data bits.
```
 ret = csi_usart_config(usart, 115200, USART_MODE_ASYNCHRONOUS, USART_PARITY_NONE, USART_STOP_BITS_1, USART_DATA_BITS_8);
```

Then you have successfully configured USART. But before use, you need to create a call back function appeared in step 2 usart_event_cb which deals with interrupt callback code, i.e. However, it does not matter if you make it an empty function if you would like to process this callback event in your main function.

 /******************************************************************************
 * @brief      UART interrupt event call back function prototype for wujian100
 * @param[in]  idx     usart port to operate.
 * @param[in]  event   event type.
 * @author     Jiayi
 * @return     None
 ******************************************************************************/
 static void usart_event_cb(int32_t idx, uint32_t event)
 {
     uint8_t g_data[15];

     switch (event) {
         case USART_EVENT_SEND_COMPLETE:
             tx_async_flag = 1;
             break;

         case USART_EVENT_RECEIVE_COMPLETE:
             rx_async_flag = 1;
             break;

         case USART_EVENT_RECEIVED:
             csi_usart_receive_query(g_usart_handle, g_data, 15);

         default:
             break;
     }
 }

How to use UART to output or input? Just use printf function and fgetc function since board_init file has helped us with the function remapping. For more details please refer to Part4_Hello_World.
I would come up with more about USART usage in the future.

FPGA Development with wujian100 SoC - Part Five: GPIO

Mon, 06 Apr 2020 01:00:25 +0000

Control general-purpose input/output (GPIO) port with wujian100 SoC.

FPGA Development with wujian100 SoC

Part Five: GPIO (LED ON and OFF)

Author: 加一(Jiayi)

Something to say

About WJ100

According to the official sites of t-head Inc., WJ100 is a low cost and high power efficiency SoC, which barely means that it could be easily deployed on any chips and consumes lower power.

related websites t-head

How to use WJ100 SoC

This tutorial is for those who utilize vivado to generate bitstream file and CDK to develop your own projects on Windows.

For Part 1 Bitsream Generation please refer to Part_1_Bitstream_Generation.
For Part 2 CDK Toolkit and wujian100 SDK please refer to Part_2_CDK_Toolkit&Wujian100_SDK.
For Part 3 Start a New Project on CDK please refer to Part_3_Start_a_New_Project_on_CDK
For Part 4 Hello World please refer to Part4_Hello_World
For Part 5 GPIO please refer to Part5_GPIO
For Part 6 UART please refer to Part6_UART
For Part 7 TIMER please refer to Part7_TIMER
For Part 8 Interrupt please refer to Part8_VIC

Part 5 GPIO

1 What is GPIO

To be brief, GPIO is what we use to write or read digital High/Low signal to and from.

2 Let us see what we have got in library

Open drv_gpio.h, as we could see in the following external functions that we could call. They are expained quite elaborate by t-head Inc..

/**
  \brief       Initialize GPIO handle.
  \param[in]   gpio_pin    gpio pin idx.
  \param[in]   cb_event  event callback function \ref gpio_event_cb_t
  \return      gpio_pin_handle
*/
gpio_pin_handle_t csi_gpio_pin_initialize(int32_t gpio_pin, gpio_event_cb_t cb_event);

/**
  \brief       De-initialize GPIO pin handle.stops operation and releases the software resources used by the handle.
  \param[in]   handle    gpio pin handle to operate.
  \return      error code
*/
int32_t csi_gpio_pin_uninitialize(gpio_pin_handle_t handle);

/**
  \brief       control gpio power.
  \param[in]   handle  gpio handle to operate.
  \param[in]   state   power state.\ref csi_power_stat_e.
  \return      error code
*/
int32_t csi_gpio_power_control(gpio_pin_handle_t handle, csi_power_stat_e state);

/**
  \brief       config pin mode
  \param[in]   pin       gpio pin handle to operate.
  \param[in]   mode      \ref gpio_mode_e
  \return      error code
*/
int32_t csi_gpio_pin_config_mode(gpio_pin_handle_t handle,
                                 gpio_mode_e mode);

/**
  \brief       config pin direction
  \param[in]   pin       gpio pin handle to operate.
  \param[in]   dir       \ref gpio_direction_e
  \return      error code
*/
int32_t csi_gpio_pin_config_direction(gpio_pin_handle_t handle,
                                      gpio_direction_e dir);

/**
  \brief       config pin
  \param[in]   pin       gpio pin handle to operate.
  \param[in]   mode      \ref gpio_mode_e
  \param[in]   dir       \ref gpio_direction_e
  \return      error code
*/
int32_t csi_gpio_pin_config(gpio_pin_handle_t handle,
                            gpio_mode_e mode,
                            gpio_direction_e dir);

/**
  \brief       Set one or zero to the selected GPIO pin.
  \param[in]   pin       gpio pin handle to operate.
  \param[in]   value     value to be set
  \return      error code
*/
int32_t csi_gpio_pin_write(gpio_pin_handle_t handle, bool value);

/**
  \brief       Get the value of  selected GPIO pin.
  \param[in]   pin       gpio pin handle to operate.
  \param[out]  value     buffer to store the pin value
  \return      error code
*/
int32_t csi_gpio_pin_read(gpio_pin_handle_t handle, bool *value);

/**
  \brief       set GPIO interrupt mode.
  \param[in]   pin       gpio pin handle to operate.
  \param[in]   mode      irq mode to be set
  \param[in]   enable    enable flag
  \return      error code
*/
int32_t csi_gpio_pin_set_irq(gpio_pin_handle_t handle, gpio_irq_mode_e mode, bool enable);

3 How to use these functions

Now we have reached to the high points of this article, the use of GPIO in wujian100 SoC.

Unitialize the GPIO in case pre-configuration has been done unpurposely.
```
 csi_gpio_pin_uninitialize(gpio_pin_handle_t pin);
```
Initialize the GPIO function by port directly since wujian100 official offers only one single port.
```
 pin = csi_gpio_pin_initialize(gpio_pin, gpio_interrupt_handler);
```
Set GPIO pin mode. There are 5 modes for us to choose.

Three for input: GPIO_MODE_PULLNONE,GPIO_MODE_PULLUP and GPIO_MODE_PULLDOWN

Two for output: GPIO_MODE_OPEN_DRAIN and GPIO_MODE_PUSH_PULL

For more knowledge about GPIO mode, please refer to embeddedartistry by PHILLIP JOHNSTON.

In this case we set mode as push pull used for output.
```
 csi_gpio_pin_config_mode(pin, GPIO_MODE_PUSH_PULL);
```
Set the GPIO direction as Output/Input whatever you would like it to be. In this case, well, we set it as Output since I have nothing to input.
```
 csi_gpio_pin_config_direction(pin, GPIO_DIRECTION_OUTPUT);
```

After configuration, we might need to output value to the port.

 csi_gpio_pin_write(pin, 1); //write pin with high voltage level
 csi_gpio_pin_write(pin, 0); //write pin with low voltage level

If you would like to read from a pin. Be sure to prepare a bool buffer, i.e. bool val; and read from pin using
```
 csi_gpio_pin_read(pin, &val);
```

FPGA Development with wujian100 SoC - Part Four: Hello World

Tue, 31 Mar 2020 01:00:25 +0000

Print Hello World with wujian100 SoC.

FPGA Development with wujian100 SoC

Part Four: Hello World

Author: 加一(Jiayi)

Something to say

About WJ100

According to the official sites of t-head Inc., WJ100 is a low cost and high power efficiency SoC, which barely means that it could be easily deployed on any chips and consumes lower power.

related websites t-head

How to use WJ100 SoC

This tutorial is for those who utilize vivado to generate bitstream file and CDK to develop your own projects with Windows.

For Part 1 Bitsream Generation please refer to Part_1_Bitstream_Generation.
For Part 2 CDK Toolkit and wujian100 SDK please refer to Part_2_CDK_Toolkit&Wujian100_SDK.
For Part 3 Start a New Project on CDK please refer to Part_3_Start_a_New_Project_on_CDK
For Part 4 Hello World please refer to Part4_Hello_World
For Part 5 GPIO please refer to Part5_GPIO
For Part 6 UART please refer to Part6_UART
For Part 7 TIMER please refer to Part7_TIMER
For Part 8 Interrupt please refer to Part8_VIC

Part 4 Hello World

After all that sruggles before, now we could finally write our programs by using CDK which is relatively simple if you have some background knowledge about working on Microprocessor, say STM32, Arduino or so. Let us strat with s simple Hello World project.

1 Open project

Open the cdk project we just built in Part 3. And open main.c Under folder main.

2 Main function

Since it is an exclusively simple file, I would skip to expain what’s what. However, you may have some probelm why printf function could make an output and where does this string goes to.

/******************************************************************************
* @file     main.c
* @brief    hello world
* @version  V1.0
* @date     31. Mar. 2020
******************************************************************************/

#include <stdio.h>

int main(void)
{
    printf("Hello World!\n --example by jiayi\n");

    return 0;
}

3 Why this simple

To reveal where printf function remaps, open board_init.c under path ./board/wujian100_open_evb as we could see below.

void board_init(void)
{
    int32_t ret = 0;
    /* init the console*/
    clock_timer_init();
    clock_timer_start();

    console_handle = csi_usart_initialize(CONSOLE_IDX, NULL);
    /* config the UART */
    ret = csi_usart_config(console_handle, 115200, USART_MODE_ASYNCHRONOUS, USART_PARITY_NONE, USART_STOP_BITS_1, USART_DATA_BITS_8);

    if (ret < 0) {
        return;
    }
}

usart is initiallized. And also, timer is initialized to make delay functionale.

4 Let us dig deeper

To dig deeper, right click variable console_handle and goto implementation. We could find this variable is defined in minilibc_port.c which gives a mapping function from usart to fputc and fgetc which make it easier to programm

int fputc(int ch, FILE *stream)
{
    (void)stream;

    if (console_handle == NULL) {
        return -1;
    }

    if (ch == '\n') {
        csi_usart_putchar(console_handle, '\r');
    }

    csi_usart_putchar(console_handle, ch);

    return 0;
}

int fgetc(FILE *stream)
{
    uint8_t ch;
    (void)stream;

    if (console_handle == NULL) {
        return -1;
    }

    csi_usart_getchar(console_handle, &ch);

    return ch;
}

5 How to run this project

Open CDK project as direction above and make sure to open serial panel to receive message.
Right click on serial panel and choose settings.

Since the UART has been configured as in the functions demonstrated in 3 which is

 Baud rate: 115200 //Baud rate with 115200
 Mode: USART_MODE_ASYNCHRONOUS //mode asychronous
 Parity: USART_PARITY_NONE //not using parity flag
 Stop bits: USART_STOP_BITS_1 //1 stop bits
 Data bits: USART_DATA_BITS_8 //8 data bits

Hence we must configure the serial panel with same configuration. And do not forget to check which com port your device uses, or you could test one by one.

Click ok and you should have successfully finished your serial configuration. And your serial panel should be like
Run the project with the debugger and start debug. And as you could see below, success!

FPGA Development with wujian100 SoC - Part Three: Start a New Project on CDK

Sun, 29 Mar 2020 01:00:25 +0000

Start a new project with CDK.

FPGA Development with wujian100 SoC

Part Three: Start a New Project on CDK

Author: 加一(Jiayi)

Something to say

About WJ100

According to the official sites of t-head Inc., WJ100 is a low cost and high power efficiency SoC, which barely means that it could be easily deployed on any chips and consumes lower power.

related websites t-head

How to use WJ100 SoC

This tutorial is for those who utilize vivado to generate bitstream file and CDK to develop your own projects with Windows.

For Part 1 Bitsream Generation please refer to Part_1_Bitstream_Generation.
For Part 2 CDK Toolkit and wujian100 SDK please refer to Part_2_CDK_Toolkit&Wujian100_SDK.
For Part 3 Start a New Project on CDK please refer to Part_3_Start_a_New_Project_on_CDK
For Part 4 Hello World please refer to Part4_Hello_World
For Part 5 GPIO please refer to Part5_GPIO
For Part 6 UART please refer to Part6_UART
For Part 7 TIMER please refer to Part7_TIMER
For Part 8 Interrupt please refer to Part8_VIC

Part 3 Start a New Project on CDK

Open your CDK desktop.
Before create a new projeck, we need to create a new workspace for it. Click create a new multi-project workspace and choose your name and path. Finish the create of project.
After we have successfully created the workspace, we could now create a new project. Find Project on your toolbar and choose new project and there will be a new project window.
Since CDK doesn’t offer an template for wujian100, we must choose a core similar to wujian100 SoC. So let us choose Smartl_E902-BareMetal under ERISC Series. However, as I believe, whatever you choose are both alright because we are going to delete all the files and change almost every configuration later.
Remove every folder in the project you just created. Both in the workspace and in the folder. Be careful because you need to restore main folder and {yourprojectname}.cdkprj
Go to wujian100_open repo path and open sdk, copy following folders to ./{yourcdkprojectname}: board, csi_core, csi_driver, csi_kernel, libs, utilities. Open projects-examples-hello_world and copy config folder to ./{yourcdkprojectname}, just like:
Right click {yourprojectname} in the left side bar or wherever called project view window and choose add source folder option.
Add folders just moved to your project folder one by one and click NO for “copy source folder to current project path”.
Finally you should see the project view like this with 8 folders and all its contents are inside.
Open project menu on the toolbar and select open active project settings.
In target label under target info we could write our description about wujian100, i.e.
```
Core: wujian100 SoC
Board: Xilinx XC7A200TR3B
```

In Compiler label we need to modify include path, delete several include path related to the original template. The include path should be like the following.

$(ProjectPath)
$(ProjectPath)//configs
$(ProjectPath)/board/wujian100_open_evb/include
$(ProjectPath)/csi_core/include
$(ProjectPath)/csi_driver/include
$(ProjectPath)/csi_driver/wujian100_open/include
$(ProjectPath)/csi_kernel/include
$(ProjectPath)/csi_kernel/rhino/arch/include
$(ProjectPath)/csi_kernel/rhino/common
$(ProjectPath)/csi_kernel/rhino/core/include
$(ProjectPath)/csi_kernel/rhino/driver
$(ProjectPath)/csi_kernel/rhino/pwrmgmt
$(ProjectPath)/include
$(ProjectPath)/libs/include
$(ProjectPath)/libs/include/ringbuffer
$(ProjectPath)/libs/include/sys

In Assembler label we need also change the include path to be like following.
```
$(ProjectPath)
$(ProjectPath)//configs
```
In Linker label under link file dock, we must change that into our gcc_csky.ld file.
```
$(ProjectPath)/board/wujian100_open_evb/gcc_csky.ld
```
In User laber under Run user programm AFTER build/rebuild dock, we need to change that into our after_bd.sh
```
$(ProjectPath)/utilities/aft_build.sh
```
Click OK to end the configuration.
Build the project and finally we could see the Done message.

FPGA Development with wujian100 SoC - Part Two: CDK Toolkit and wujian100 SDK

Fri, 27 Mar 2020 01:00:25 +0000

Introduction to wujian100 sdk and CDK Toolkit.

FPGA Development with wujian100 SoC

Part Two: CDK Develop

Author: 加一(Jiayi)

Something to say

About WJ100

According to the official sites of t-head Inc., WJ100 is a low cost and high power efficiency SoC, which barely means that it could be easily deployed on any chips and consumes lower power.

related websites t-head

How to use WJ100 SoC

This tutorial is for those who utilize vivado to generate bitstream file and CDK to develop your own projects with Windows.

For Part 1 Bitsream Generation please refer to Part_1_Bitstream_Generation.
For Part 2 CDK Toolkit and wujian100 SDK please refer to Part_2_CDK_Toolkit&Wujian100_SDK.
For Part 3 Start a New Project on CDK please refer to Part_3_Start_a_New_Project_on_CDK
For Part 4 Hello World please refer to Part4_Hello_World
For Part 5 GPIO please refer to Part5_GPIO
For Part 6 UART please refer to Part6_UART
For Part 7 TIMER please refer to Part7_TIMER
For Part 8 Interrupt please refer to Part8_VIC

Part 2 CDK Develop on Windows

1. Software and Environment Installation

Prep your CDK desktop which is offered on occ-thead and you could download it directly by click CDK_V2.0.4. Its related toolchain which is offered on t-head could be download directly by click CDK_related_Software.
Install CDK V2.0.4 which is in cdk-windows-V2.0.4-20200106-2123.zip on your desktop.
Install T-Head DebugServer-V5.8.6 which is offered in T-head Tools package.zip.

2. About wujian100 sdk

THIS PART IS INDIRECTLY TRANSLATED FROM wujian100 sdk 解读

So far we have successfully install all the software we need to program on your wujian100 SoC. Next let us see what we have got in repo wujian100_open.

Open repo directory on your local computer and go into sdk folder. As we could see in the following structure

sdk
├── board
├── csi_core
├── csi_driver
├── csi_kernel
├── libs
├── projects
├── utilities
└── VERSION

board
```
board
 └─wujian100_open_evb
     │  board_init.c
     │  gcc_csky.ld
     │
     └─include
             pin.h
             test_driver_config.h
             test_kernel_config.h
```
board folder contains hardware initialize files.
- board_init.c is called before main function. It configures clock timer used as record and delay and usart used as output.
- gcc_csky.ld is the compilation link configuration, which configures the storage location of each field of the firmware generated by compilation, including i-sram, sram and heap size.
- pin.h defines pin names used in examples and test projects.
- test_driver_config.h defines enabilty for test projects.
- test_kernel_config.h defines names for rtos used in test projects.

csi_core

csi_core
 └─include
         core_rv32.h
         csi_core.h
         csi_rv32_gcc.h

csi_driver

csi_driver
 ├─include
 │      drv_aes.h
 │      drv_common.h
 │      drv_crc.h
 │      drv_dmac.h
 │      drv_eflash.h
 │      drv_errno.h
 │      drv_gpio.h
 │      drv_i2s.h
 │      drv_iic.h
 │      drv_intc.h
 │      drv_irq.h
 │      drv_pmu.h
 │      drv_pwm.h
 │      drv_rsa.h
 │      drv_rtc.h
 │      drv_sha.h
 │      drv_spi.h
 │      drv_spiflash.h
 │      drv_timer.h
 │      drv_trng.h
 │      drv_usart.h
 │      drv_wdt.h
 │
 └─wujian100_open
     │  devices.c
     │  isr.c
     │  lib.c
     │  novic_irq_tbl.c
     │  pinmux.c
     │  startup.S
     │  system.c
     │  sys_freq.c
     │  trap_c.c
     │  vectors.S
     │  wj_dmac_v2.c
     │  wj_irq.c
     │  wj_oip_gpio.c
     │  wj_oip_timer.c
     │  wj_oip_wdt.c
     │  wj_pwm.c
     │  wj_rtc.c
     │  wj_usi.c
     │  wj_usi_iic.c
     │  wj_usi_spi.c
     │  wj_usi_usart.c
     │  wj_usi_wrap.c
     │
     └─include
             drv_usi_iic.h
             drv_usi_spi.h
             drv_usi_usart.h
             io.h
             pinmux.h
             pin_name.h
             soc.h
             sys_freq.h
             usi_pin_planning.h
             wj_dmac_v2.h
             wj_oip_gpio.h
             wj_oip_timer.h
             wj_oip_wdt.h
             wj_pwm.h
             wj_rtc.h
             wj_usi.h
             wj_usi_iic.h
             wj_usi_spi.h
             wj_usi_usart.h

csi_kernel

csi_kernel
 ├─include
 │      csi_kernel.h
 │
 └─rhino
     ├─adapter
     │      csi_rhino.c
     │
     ├─arch
     │  ├─include
     │  │      k_config.h
     │  │      k_types.h
     │  │      port.h
     │  │
     │  └─riscv
     │          cpu_impl.c
     │          csky_sched.c
     │          port_c.c
     │          port_s.S
     │
     ├─board
     │      board_cpu_pwr.c
     │      board_cpu_pwr_rtc.c
     │      board_cpu_pwr_systick.c
     │      board_cpu_pwr_timer.c
     │
     ├─common
     │      k_atomic.c
     │      k_atomic.h
     │      k_cpuset.h
     │      k_ffs.c
     │      k_ffs.h
     │      k_fifo.c
     │      k_trace.c
     │
     ├─core
     │  │  k_buf_queue.c
     │  │  k_dyn_mem_proc.c
     │  │  k_err.c
     │  │  k_event.c
     │  │  k_idle.c
     │  │  k_mm.c
     │  │  k_mm_blk.c
     │  │  k_mm_debug.c
     │  │  k_mutex.c
     │  │  k_obj.c
     │  │  k_pend.c
     │  │  k_queue.c
     │  │  k_ringbuf.c
     │  │  k_sched.c
     │  │  k_sem.c
     │  │  k_stats.c
     │  │  k_sys.c
     │  │  k_task.c
     │  │  k_task_sem.c
     │  │  k_tick.c
     │  │  k_time.c
     │  │  k_timer.c
     │  │  k_workqueue.c
     │  │
     │  └─include
     │          k_api.h
     │          k_bitmap.h
     │          k_buf_queue.h
     │          k_critical.h
     │          k_default_config.h
     │          k_endian.h
     │          k_err.h
     │          k_event.h
     │          k_fifo.h
     │          k_hook.h
     │          k_internal.h
     │          k_list.h
     │          k_mm.h
     │          k_mm_blk.h
     │          k_mm_debug.h
     │          k_mm_region.h
     │          k_mutex.h
     │          k_obj.h
     │          k_queue.h
     │          k_ringbuf.h
     │          k_sched.h
     │          k_sem.h
     │          k_soc.h
     │          k_stats.h
     │          k_sys.h
     │          k_task.h
     │          k_task_sem.h
     │          k_time.h
     │          k_timer.h
     │          k_trace.h
     │          k_workqueue.h
     │
     ├─driver
     │      coretim.h
     │      hook_impl.c
     │      hook_weak.c
     │      systick.c
     │      yoc_impl.c
     │
     └─pwrmgmt
             cpu_pwr_api.h
             cpu_pwr_config.h
             cpu_pwr_hal_lib.h
             cpu_pwr_lib.h
             cpu_tickless.h
             dl_list.h
             pwr_debug.h
             pwr_state.h

libs

libs
 │  libnewlib_wrap.a
 │
 ├─include
 │  │  errno.h
 │  │  mm.h
 │  │  mm_queue.h
 │  │  syslog.h
 │  │  time.h
 │  │  umm_heap.h
 │  │
 │  ├─ringbuffer
 │  │      ringbuffer.h
 │  │
 │  └─sys
 │          _stdint.h
 │
 ├─libc
 │      clock_gettime.c
 │      malloc.c
 │      minilibc_port.c
 │      _init.c
 │
 ├─mm
 │      dq_addlast.c
 │      dq_rem.c
 │      lib_mallinfo.c
 │      mm_addfreechunk.c
 │      mm_free.c
 │      mm_initialize.c
 │      mm_leak.c
 │      mm_mallinfo.c
 │      mm_malloc.c
 │      mm_size2ndx.c
 │
 ├─ringbuffer
 │      ringbuffer.c
 │
 └─syslog
         syslog.c

projects

projects
 ├─benchmark
 │  ├─coremark
 │  │
 │  └─dhrystone
 │
 ├─examples
 │  ├─core
 │  │  └─vic
 │  │
 │  ├─driver
 │  │  ├─dmac
 │  │  │
 │  │  ├─gpio
 │  │  │
 │  │  ├─timer
 │  │  │
 │  │  ├─usart
 │  │  │
 │  │  └─wdt
 │  │
 │  ├─hello_world
 │  │
 │  └─kernel
 │      ├─event
 │      │
 │      ├─mem_pool
 │      │
 │      ├─message_q
 │      │
 │      ├─mutex
 │      │
 │      ├─sem
 │      │
 │      ├─task
 │      │
 │      ├─time
 │      │
 │      └─timer
 │
 └─tests
     └─driver

utilities

utilities
    aft_build.sh
    flash.init
    gdb.init

FPGA Development with wujian100 SoC - Part One: Bitstream Generation

Wed, 25 Mar 2020 01:00:25 +0000

Generate wujian100 SoC Bitstream file in windows with Vivado 2018.3

FPGA Development with wujian100 SoC

Part One: Bitsream Generation

Author: 加一(Jiayi)

Something to say

Recently I participated in a contest named Integrate Circuit Innovation Contest which requires me to use WJ100 developed by Ali Inc. team t-head and an FPGA develop board with Xilinx XC7A200TR3B Core. It’s not my first time to cope with FPGA but still, I find it difficult to interpret Verilog Code and make the FPGA works. Luckily, with the help of WJ100 Sdk and CDK(C-sky Develop Kit) which was developed by Ali Inc., we could jump the Verilog and long waiting synthesizing part directly to use the pre-setted circuit and easy writing C to develop.

About WJ100

According to the official sites of Pinhead Inc., WJ100 is a low cost and high power efficiency SoC, which barely means that it could be easily deployed on any chips and consumes lower power.

However, as I talked before, it is an open-source project and as I believed, the real function of this SoC is to simplify the use of FPGA and to offer the developer a brand new way to develop: integrate Soc and FPGA to deal with some projects which require both power efficiency and fast steady frequency.

related websites t-head

How to use WJ100 SoC

This tutorial is for those who utilize Vivado to generate bitstream file and CDK to develop your projects with Windows. This tutorial is for those who utilize Vivado to generate bitstream file and CDK to develop your projects with Windows.

For Part 1 Bitsream Generation please refer to Part_1_Bitstream_Generation.
For Part 2 CDK Toolkit and wujian100 SDK please refer to Part_2_CDK_Toolkit&Wujian100_SDK.
For Part 3 Start a New Project on CDK please refer to Part_3_Start_a_New_Project_on_CDK
For Part 4 Hello World please refer to Part4_Hello_World
For Part 5 GPIO please refer to Part5_GPIO
For Part 6 UART please refer to Part6_UART
For Part 7 TIMER please refer to Part7_TIMER
For Part 8 Interrupt please refer to Part8_VIC

Part 1 Bitstream Generation

clone wujian100_open project into your computer with git bash or GitHub. Or just download and unzip it.

As demonstrated by readme.md in wujian100_open repo, the structure of this repo is as following

 Directory Structure
 |--Project                //open source project work directory  
 |--riscv_toolchain      //tool chain install directory download from t-head.cn
 |--wujian100_open       //wujian100_open project get from github
     |--case               //test case example for simulation
     |--doc                //wujian100_open user guide
     |--fpga               //FPGA script
     |--lib                //compile script for simulation
     |--regress            //regression result
     |--sdk                //software design kit
     |--soc                //Soc RTL source code
     |--tb                 //test bench
     |--tools              //simulation script and setup file
     |--workdir            //simulation directory
     |--LICENSE
     |--README.md

according to this structure what we need for bitstream generation is in the soc and fpga folder.

THE FOLLOWING PARTS 3. – ARE INDIRECTLY INTERPRETED FROM wujian100_open的FPGA实现——如何用vivado生成wujian100_open的比特流文件 CHINESE DEVELOPER COULD DIRECTLY LOOK UP IN THIS PAGE. THANK Lianglonghui FOR HIS SHARING

Prep your Vivado, I use Vivado 2018.3, but as I believe the newer or older versions could also work, the demonstration all runs in Vivado 2018.3 HLX Edition and Windows 10.
1. Open your Vivado and create a new RTL project.
2. Add source directory ./wujian100_open/soc and wujian100_open_fpga_top.v in directory ./wujian100_open/fpga.
3. Check Scan and add RTL files into project, copy source into project, and add sources from subdirectory.
4. Add constrain file XC7A200T3B in directory ./wujian100_open/fpga/xdc and check copy constrain into project
5. Search device XC7A200TFBG484-2L in Part menu
6. Finish create and the guide should be like
7. After Vivado has created the project, as we could see, there might be 4 syntax error files, which is due to the wrong file type. Hence we should correct it manually by right click every error file and choose source file property and change its property into verilog header as following.
8. As we add our sources by adding a directory, we actually added a redundant source file. We need to remove the file wujian100_open_top.v.
9. After removing the file, we could set the top file wujian100_open_fpga_top.v to be the first to compile.
  - TWO important STEP
10. Since the constrain file did not constrain the clock, we must add the following xdc code into the file XC7A200T3B.xdc
```
create_clock -name {EHS} [get_ports PIN_EHS] -period 50 -waveform {0 25}
create_clock  -name {JTAG_CLK} [get_ports PAD_JTAG_TCLK] -period 1000 -waveform {0 500}

set_clock_groups -asynchronous -name {clkgroup_1} -group [get_clocks {EHS JTAG_CLK}]

set_false_path -through [get_ports PIN_EHS]

#set_clock_groups -name {Inferred_clkgroup_0} -asynchronous -group [get_clocks {wujian100_open_top|PAD_JTAG_TCLK}]

set_property ASYNC_REG TRUE [get_cells {x_aou_top/x_rtc0_sec_top/x_rtc_pdu_top/x_rtc_clr_sync/pclk_load_sync2_reg}]
set_property ASYNC_REG TRUE [get_cells {x_aou_top/x_rtc0_sec_top/x_rtc_pdu_top/x_rtc_clr_sync/rtc_load_sync2_reg}]
set_property ASYNC_REG TRUE [get_cells {x_aou_top/x_rtc0_sec_top/x_rtc_pdu_top/x_rtc_clr_sync/pclk_load_sync1_reg}]
set_property ASYNC_REG TRUE [get_cells {x_aou_top/x_rtc0_sec_top/x_rtc_pdu_top/x_rtc_clr_sync/rtc_load_sync1_reg}]
set_property ASYNC_REG TRUE [get_cells {x_cpu_top/CPU/x_cr_had_top/A15d/A74/A10b_reg}]
set_property ASYNC_REG TRUE [get_cells {x_cpu_top/CPU/x_cr_had_top/A15d/A74/A18597_reg}]
set_property ASYNC_REG TRUE [get_cells {x_cpu_top/CPU/x_cr_had_top/A15d/A1862d/A10b_reg}]
set_property ASYNC_REG TRUE [get_cells {x_cpu_top/CPU/x_cr_had_top/A15d/A1862d/A18597_reg}]
set_property ASYNC_REG TRUE [get_cells {x_cpu_top/CPU/x_cr_had_top/A15d/A75/A10b_reg}]
set_property ASYNC_REG TRUE [get_cells {x_cpu_top/CPU/x_cr_had_top/A15d/A75/A18597_reg}]
```
11. change one name from get_nets PAD_JTAG_TCLK_c into get_nets PAD_JTAG_TCLK. i.e.,
```
   # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets PAD_JTAG_TCLK_c]
   into
   set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets PAD_JTAG_TCLK]
```
12. Generate Bitstream and watch two sets of Rick and Morty since it costs me 31 minutes to finish the bitstream writing.
13. Finally we receive the success message. Find your wujian100_open_top.bit file in directory ./{your_project_name}.runs/impl_1}. And change the file name into cfg.bit.
14. Copy your cfg.bit file into your FPGA. Check if it works.(First-time configuration may fail. Just press re-prog one another time)

Hello Blog

Wed, 25 Mar 2020 01:00:00 +0000

How to build a personal blog with Github pages.

Something to say

After meeting many obstacles, I copied a repository from qiubaiying.

The original repository is https://github.com/qiubaiying/qiubaiying.github.io

Currently I am using theme by walterlv(Lv Yi)

Although I know nothing about html and little about GitHUb.

Or more critically, I am learning German right now.

SO everytime I start writing something with English, German jumps out and vice versa.

The reason why I start my blog is that I think it’s time to sort my codes and projects out

Process

I will briefly describe the way I did to build this Blog.

1. github part

Firstly, with the help of qiubaiying, i mean his Blog. 博客搭建详细教程

I could barely understand where to put tiles and how to make it work.

But things get difficult when I was trying to reach github.com since its DNS got polluted by GFW.

1* accelerate github access

It takes me a few minutes to deal with that. And specific solution could be found in 国内加速访问Github的办法，超级简单.

This way is basically changing the pin address of domain in China by modifying the host.

By the time 2020/3/24 21:00 GMT+8, the hosts are as following:

82.112.4 github.com

199.108.153 assets-cdn.github.com

232.5.194 github.global.ssl.fastly.net

216.93.131 github-cloud.s3.amazonaws.com

2. jekyll part

Secondly, as I am writing this post, wierd thing comes up that the page i pushed does not appear on my site.

Then I realize that this process may related with jekyll and i go back to install jekyll on Windows.

The tutorial for jekyll is jekyll on windows

which required for something called Chocolatey

After seveal command lines, i mean a lot of ones. (i am still waiting for the installation so that i could write this post)

I am quite curious that with 300Mb internet bandwidth it still takes like a year to download a 40Mb-file.

And some other wierd things come up, saying “ERROR: Could not find a valid gem ‘nokogiri’ (>= 0), here is why: Unable to download data from https://rubygems.org/ - SSL_connect returned=1 errno=0 state=SSLv3 read server certificate B: certificate verify failed (https://api.rubygems.org/specs.4.8.gz)”

It seems like i have not proper SSL to download nokogiri and after googling for the solution, i decide to take another approach which demonstrated on https://jekyllrb.com/docs/installation/windows/

As i was checking my wechat message, the installation finished and finally it works.

3. How to use Jekyll

Finally, I managed to set up Jekyll environment on my windows 10. And it seems a little bit intrige to use Jekyll since I an a little white and know nothing about bash except some simple linux commandlines, however, it really helps (:.

3.1 Basic commands

The first thing to do is open your cmd.exe with win+R or windows powershell and go into the repo directory.

cd {your repository directory}

Then you could run jekyll and see if it works using jekyll and if it shows as following, it proves working.

A subcommand is required.
jekyll 4.0.0 -- Jekyll is a blog-aware, static site generator in Ruby

Usage:

  jekyll <subcommand> [options]

Options:
        -s, --source [DIR]  Source directory (defaults to ./)
        -d, --destination [DIR]  Destination directory (defaults to ./_site)
            --safe         Safe mode (defaults to false)
        -p, --plugins PLUGINS_DIR1[,PLUGINS_DIR2[,...]]  Plugins directory (defaults to ./_plugins)
            --layouts DIR  Layouts directory (defaults to ./_layouts)
            --profile      Generate a Liquid rendering profile
        -h, --help         Show this message
        -v, --version      Print the name and version
        -t, --trace        Show the full backtrace when an error occurs

Subcommands:
  compose
  docs
  import
  build, b              Build your site
  clean                 Clean the site (removes site output and metadata file) without building.
  doctor, hyde          Search site and print specific deprecation warnings
  help                  Show the help message, optionally for a given subcommand.
  new                   Creates a new Jekyll site scaffold in PATH
  new-theme             Creates a new Jekyll theme scaffold
  serve, server, s      Serve your site locally

Codes above also shows what basic commands for Jekyll are.

3.2 Getting Start

Fork your favourite theme from wiki of Jekyll
Clone the repo into your computer(optional since i live in China and the github connection sucks). Because i use github desktop, it would not be any problem to clone and push.
Open folder _posts and there should be some examples, if not, create one with name must be in the correct form.
- yyyy-mm-dd-title.md example: ‘2020-03-24-example.md’

Open the file you just created with code or notepad. And add some headings required by the theme. My headings are, for example but not always be effective in your repo.

 ---
 layout:     post
 title:      My First Blog on Github.io
 subtitle:    "\"Hello World, Hello Blog\""
 date:       2020-03-24
 author:     BY
 header-img: img/what-is-a-blog.png
 catalog: true
 tags:
     - Blog Build
 ---

which specifies the layout, title, date and auther required by my theme.

Write your post with markdown and you could also download code extensions for Markdown language. It’s basically a easy language of text editing and you could find how to write that in markdown_wikipedia.
Save the text and go back to windows command line, i.e. cmd or powershell whatever you just used to check jekyll.
Run command jekyll build --w which i prefer to use --w or --watch meaning to monitor all changes in the file so that i can preview without run more commands.
Before STEP 7 you may need to run command jekyll serve or jekyll s which enables you to build the serve on your local computer and see your web on your browser in localhost.
Finally, after all the editing, push your repo onto github, after few minutes you may see your Blog article on your github.io.

shieldjy

NeuroSim Part 1

About This Project

Running the Instance

FPGA Development with wujian100 SoC - Part Ten: Add On-Board Buttons to SoC

FPGA Development with wujian100 SoC

Part Ten: Add On-Board Buttons to SoC

Something to say

About WJ100

How to use WJ100 SoC

Part 10 Add On-Board Buttons to SoC

FPGA Development with wujian100 SoC - Part Nine: Working on Bugs

FPGA Development with wujian100 SoC

Part Nine: Working on Bugs

Something to say

About WJ100

How to use WJ100 SoC

Part 9 Bugs Issue

001 return problem

SoC on FPGA - Part One: Overview

System on Chip (SoC)

Field-Programmable Gate Array (FPGA)

Dynamic Random Access Memory

1. What is DRAM

2. Structure of DRAM Cells

3. Latest researches on DRAM

Volatile

Float Body Cell (FBC) Structure for 1T-DRAM

Non-Volatile

Inorganic Non-Volatile Memory Cells

Organic Non-Volatile Memory Cells

Reference

FPGA Development with wujian100 SoC - Part EIGHT: Interrupt(VIC)

FPGA Development with wujian100 SoC

Part EIGHT: Interrupt (VIC)

Something to say

About WJ100

How to use WJ100 SoC

Part 8 Interrupt

1 What is Interrupt

2 What is VIC

3 How does interrupt work

4 What do we get in wujian100

However, IRQ interrupt priority is strongly advised to prevent some sequence error, since t-head Inc. does not offer us official paper about default IRQ sequence.

5 How to use VIC

FPGA Development with wujian100 SoC - Part SEVEN: TIMER

FPGA Development with wujian100 SoC

Part SEVEN: TIMER

Something to say

About WJ100

How to use WJ100 SoC

Part 7 TIMER

1 What is Timer

2 Let us see what we have got in library

3 How to use these functions

FPGA Development with wujian100 SoC - Part Six: UART

FPGA Development with wujian100 SoC

Part Six: UART

Something to say

About WJ100

How to use WJ100 SoC

Part 6 UART

1 What is UART

2 Let us see what we have got in library

3 How to use these functions

FPGA Development with wujian100 SoC - Part Five: GPIO

FPGA Development with wujian100 SoC

Part Five: GPIO (LED ON and OFF)

Something to say

About WJ100

How to use WJ100 SoC

Part 5 GPIO

1 What is GPIO

2 Let us see what we have got in library

3 How to use these functions

FPGA Development with wujian100 SoC - Part Four: Hello World

FPGA Development with wujian100 SoC

Part Four: Hello World

Something to say

About WJ100

However, IRQ interrupt priority is `strongly advised` to prevent some sequence error, since t-head Inc. does not offer us official paper about default IRQ sequence.